Test interconnect for bumped semiconductor components and method of fabrication

ABSTRACT

An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a support member over the recess configured to electrically engage a bumped contact. The support member is suspended over the recess on spiral leads formed on a surface of the substrate. The spiral leads allow the support member to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the spiral leads twist the support member relative to the bumped contact to facilitate penetration of oxide layers thereon. The spiral leads can be formed by attaching a polymer substrate with the leads thereon to the substrate, or by forming a patterned metal layer on the substrate. In an alternate embodiment contact, the support member is suspended over the surface of the substrate on raised spring segment leads.

FIELD OF THE INVENTION

[0001] This invention relates generally to the manufacture and testingof semiconductor components. More particularly, this invention relatesto an interconnect for electrically engaging bumped semiconductorcomponents.

BACKGROUND OF THE INVENTION

[0002] Semiconductor components, such as bare dice, chip scale packages,BGA devices and wafers can include terminal contacts in the form ofbumped contacts. This type of component is sometimes referred to as a“bumped” component (e.g., bumped die, bumped wafer).

[0003] The bumped contacts provide a high input/output capability for acomponent, and permit the component to be surface mounted, oralternately flip chip mounted, to a mating substrate, such as a printedcircuit board (PCB). Typically, the bumped contacts comprise solderballs, which permits the components to be bonded to the mating substrateusing a solder reflow process. For some components, such as chip scalepackages and BGA devices, the bumped contacts can be arranged in a densearray, such as a ball grid array (BGA), or a fine ball grid array(FBGA).

[0004] For performing test procedures on bumped semiconductor componentsit is necessary to make temporary electrical connections with the bumpedcontacts. Different types of interconnects have been developed formaking these electrical connections. For example, a wafer probe card isone type of interconnect that is used to test semiconductor wafers.Another type of interconnect, is contained within a carrier fortemporarily packaging singulated components, such as bare dice and chipscale packages, for test and burn-in. The interconnects include contactsthat make the electrical connections with bumped contacts.

[0005] One problem with making these temporary electrical connections isthat the sizes of the bumped contacts on a component can vary. Somebumped contacts can have a larger diameter and a greater height thanother bumped contacts on the same component. Also, if the interconnectis used to test different components the sizes of the bumped contactscan vary between components. The interconnect contacts may not be ableto accommodate these size differences, making reliable electricalconnections difficult to make. This problem is compounded because theinterconnect contacts must penetrate native oxide layers on the bumpcontacts to make low resistance electrical connections.

[0006] Another problem with bumped contacts particularly solder balls,is that the contacts deform easily during handling and testing,especially at elevated temperatures. For performing test procedures, itmay be difficult to make low resistance electrical connections withdeformed contacts. Specifically, the contacts on the interconnect maynot adequately engage and penetrate the surfaces of the bumped contactsunless large contact forces are employed. However, the large contactforces can also deform the bumped contacts. For subsequent bondingprocedures, deformed contacts can make alignment and bonding of thecomponent with a mating substrate more difficult. In addition, deformedcontacts are a cosmetic problem that can adversely affect a usersperception of a semiconductor component.

[0007] The present invention is directed to an interconnect for makingtemporary electrical connections with semiconductor components havingbumped contacts. The interconnect includes contacts constructed toelectrically engage the bumped contacts, and to accommodate variationsin the size and planarity of the bumped contacts.

SUMMARY OF THE INVENTION

[0008] In accordance with the present invention, an improvedinterconnect for testing bumped semiconductor components, a method forfabricating the interconnect, and test systems incorporating theinterconnect, are provided. The interconnect includes a substrate and aplurality of flexible contacts on the substrate for electricallyengaging bumped contacts on a component under test. The interconnectalso includes conductors formed on surfaces of the substrate, andconductive vias formed within the substrate, in electrical communicationwith the flexible contacts and with external contacts on the substrate.

[0009] The flexible contacts are formed on the substrate in a pattern,such as a dense grid array, that matches a pattern of the bumpedcontacts on the component. A first embodiment contact comprises a recessin the substrate, and a support member suspended on the recess forsupporting a mating bumped contact on the component. A plurality ofcantilevered leads support the support member, and are shaped to allowthe support member to move in a z-direction into the recess duringelectrical engagement of the bumped contact. The cantilevered leads havea spiral or twisted configuration similar to impeller vanes on acentrifugal pump. As the support member and bumped contact are movedinto the recess by an external biasing force, the cantilevered leadsfunction as torque springs. In addition, the leads twist the supportmember relative to the bumped contact to facilitate penetration of oxidelayers thereon.

[0010] A second embodiment flexible contact comprises a raised supportmember suspended over the substrate on spring segment leads. The springsegment leads have a spiral or twisted configuration that allows thesupport member to move towards the substrate, and to twist relative tothe bumped contact.

[0011] The support member can comprise a ring with an opening having aperipheral edge for penetrating the bumped contact. Alternately, thesupport member can comprise a solid plate having one or more penetratingprojections, for penetrating the bumped contact. In addition, thecantilevered leads, or the spring segment leads, can have a serpentineconfiguration to allow extension thereof during movement of the supportmember into the recess. Preferably, the support member comprises anon-bonding metal, or includes an outer layer that will not bond to thebumped contact. For example, for a bumped contact formed of solder, thesupport member can include a non-solder wettable outer layer.

[0012] The first embodiment contacts can be fabricated by formingrecesses in the substrate, forming the conductors and conductive vias inthe substrate, and then attaching a separate polymer film having thecantilevered leads thereon to the conductors. Alternately, the firstembodiment contacts can be fabricated by forming recesses in thesubstrate, forming resist layers in the recesses, depositing a metallayer on the substrate and resist layers, patterning the metal layer toform the support member and cantilevered leads, and then removing theresist layers in the recesses.

[0013] The second embodiment contacts can be fabricated by formingpolymer bumps on the substrate, forming the conductors on the substrateand conductive vias in the substrate, forming metal layers on thepolymer bumps, etching the metal layers to form the support member andspring segment leads, and then removing the polymer bumps.

[0014] For fabricating a die level test system, the interconnect can beconfigured for use with a test carrier configured to retain discretesemiconductor components, such as bare dice and packages, for electricalconnection to test circuitry. For fabricating a wafer level test system,the interconnect can be configured for use with a wafer proberconfigured to apply test signals to dice contained on a semiconductorwafer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1A is a schematic plan view of an interconnect constructed inaccordance with the invention;

[0016]FIG. 1B is a side elevation view of FIG. 1A;

[0017]FIG. 2A is an enlarged portion of FIG. 1A taken along section line2A-2A illustrating a contact on the interconnect;

[0018]FIG. 2B is an enlarged cross sectional view taken along sectionline 2B-2B of FIG. 2A;

[0019]FIG. 2C is an enlarged cross sectional view taken along sectionline 2C-2C of FIG. 2B;

[0020]FIG. 2D is an enlarged cross sectional view taken along sectionline 2D-2D of FIG. 2A;

[0021]FIG. 3A is an enlarged cross sectional view equivalent to FIG. 2Billustrating the contact electrically engaging a bumped contact on asemiconductor component;

[0022]FIG. 3B is an enlarged cross sectional view equivalent to FIG. 3Aillustrating the contact flexing during electrical engagement of thebumped contact;

[0023]FIG. 4A is an enlarged plan view equivalent to FIG. 2Aillustrating an alternate embodiment of the contact of FIG. 2A;

[0024]FIG. 4B is an enlarged cross sectional view taken along sectionline 4B-4B of Figure of FIG. 4A;

[0025]FIG. 4C is an enlarged plan view equivalent to FIG. 2Aillustrating another alternate embodiment of the contact of FIG. 2A;

[0026]FIG. 4D is an enlarged cross sectional view taken along sectionline 4D-4D of FIG. 4C;

[0027]FIG. 5A is an enlarged portion of FIG. 1A taken along section line5A illustrating an alternate embodiment contact on the interconnect;

[0028]FIG. 5B is an enlarged cross sectional view taken along sectionline 5B-5B of FIG. 5A;

[0029] FIGS. 6A-6E are schematic cross sectional views illustratingsteps in a method for fabricating the contact of FIG. 2A-2B;

[0030]FIG. 6F is a plan view taken along section line 6F-6F of FIG. 6B;

[0031]FIG. 6G is a plan view taken along section line 6G-6G of FIG. 6E;

[0032] FIGS. 7A-7E are schematic cross sectional views illustratingsteps in a method for fabricating an alternate embodiment contact;

[0033]FIG. 7F is a plan view taken along section line 7F-7F of FIG. 7B;

[0034]FIG. 7G is a plan view taken along section line 7G-7G of FIG. 7C;

[0035]FIG. 7H is a plan view taken along section line 7H-7H of FIG. 7E;

[0036] FIGS. 8A-8F are schematic cross sectional views illustratingsteps in a method for fabricating the contact of FIGS. 5A-5B;

[0037]FIG. 8G is a plan view taken along section line 8G-8G of FIG. 8C;

[0038]FIG. 8H is a plan view taken along section line 8H-8H of FIG. 8E;

[0039]FIG. 8I is a plan view taken along section line 8I-8I of FIG. 8F;

[0040]FIG. 9A is an exploded schematic perspective view of a testcarrier that includes an interconnect constructed in accordance with theinvention;

[0041]FIG. 9B is a schematic perspective view of the assembled testcarrier;

[0042]FIG. 9C is an enlarged schematic cross sectional view, with partsremoved, of the test carrier taken along section line 9C-9C of FIG. 9B;

[0043]FIG. 10 is a schematic cross sectional view of a wafer level testsystem incorporating an interconnect constructed in accordance with theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] Referring to FIG. 1A, an interconnect 10 constructed inaccordance with the invention is illustrated. The interconnect 10includes a substrate 12, and a pattern of contacts 14A or 14B formed onthe substrate 12. The contacts 14A or 14B are adapted to electricallyengage bumped contacts 16 (FIG. 3A) formed on land pads 28 (FIG. 3A) ona semiconductor component 18 (FIG. 3A).

[0045] As used herein, the term “semiconductor component” refers to anelectronic component that includes a semiconductor die. Exemplarysemiconductor components include bare semiconductor dice, chip scalepackages, ceramic or plastic semiconductor packages, BGA devices,semiconductor wafers, and panels containing multiple chip scalepackages.

[0046] For illustrative purposes, two different contact embodiments areillustrated in FIG. 1. However, in actual practice the interconnect 10will contain only one type of contact, either contact 14A, or contact14B. Also for illustrative purposes, only one contact for eachembodiment is illustrated on the interconnect 10. However, in actualpractice the interconnect 10 will contain enough contacts 14A or 14B toelectrically engage all of the bumped contacts 16 (FIG. 3A) on thecomponent 18 (FIG. 3A) at the same time. In addition, a pattern of thecontacts 14A or 14B will exactly match a pattern of the bumped contacts16 (FIG. 3A) on the component 18 (FIG. 3A). For example, if the bumpedcontacts 16 are formed on the component 18 in a dense array, such as aball grid array (BGA), the contacts 14A or 14B will have a correspondingdense grid array.

[0047] Referring to FIGS. 2A-2D, the first embodiment contact 14Acomprises a recess 20A in the substrate 12, a support member 21Asuspended over the recess 20A, and a plurality of cantilevered leads 22Afor supporting the support member 21A over the recess 20A. As will befurther explained, the support member 21A and cantilevered leads 22A areformed on a separate polymer film 23 (FIG. 2B) attached to the substrate12 using a conductive polymer layer 25. In addition, the contact 14A isconfigured to compensate for variations in the size (e.g., diameter,height), shape, and planarity of the bumped contacts 16 (FIG. 3A) on thecomponent 18 (FIG. 3A).

[0048] The substrate 12 can comprise a semiconductor material such asmonocrystalline silicon, germanium, silicon-on-glass, orsilicon-on-sapphire. In addition, an electrically insulating layer 24A(FIG. 2B) can be formed on exposed surfaces of the substrate 12 andwithin the recess 20A for electrically insulating the contact 14A from abulk of the substrate 12. However, as will be further explained, thesubstrate 12 can also comprise an electrically insulating material, suchas ceramic or plastic, such that electrically insulating layers are notbe required. Exemplary plastics include epoxy novolac resin, silicone,phenylsilane and thermoset plastics.

[0049] The recess 20A can be formed in the substrate 12 using an etchingprocess, a laser machining process or a molding process. In theembodiment illustrated in FIG. 2A-2D, the recess 20A is generally squareshaped, and the contact 14A includes four cantilevered leads 22A.Alternately the recess 20A can have other shapes, such as rectangular,circular, or oval. The recess 20A is sized and shaped to retain andcenter the bumped contacts 16.

[0050] As shown in FIG. 2B, the recess 20A has a width W and a depth X.The width W and depth X are approximately equal to the diameter andheight of the bumped contacts 16. Preferably, the diameter W of therecess 20A is equal to, or greater than, a diameter of the bumpedcontacts 16. A representative range for the width W can be from 2 milsto 50 mils. In addition, the depth X (FIG. 2B) of the recess 20A can beselected such that the support member 21A, can move in the z-directionwithin the recess 20A, by a distance sufficient to accommodatevariations in the size, shape and planarity of the bumped contacts 16.For example, the depth X of the recess 20A can be equal to, or lessthan, a height of the bumped contacts 16. A representative range for thedepth X can be from 1 mils to 25 mils.

[0051] As shown in FIG. 2A, the support member 21A is generally circularin shape. The support member 21A can be formed integrally with the leads22A and of a same metal as the leads 22A. The support member 21Aincludes a circular opening 26A sized to retain the bumped contact 16(FIG. 3A). In addition, the opening 26A includes a peripheral edge 27Aconfigured to penetrate the bumped contact 16 (FIG. 3A) as the supportmember 21A moves into the recess 20A.

[0052] With the contact 14A, there are four leads 22A equally angularlyspaced along a periphery of the support member 21A. Also, the leads 22Aare twisted in a clock wise direction relative to a longitudinal axis29A (FIG. 2B) of the contact 14A. The configuration of the leads 22A issimilar to the vanes of an impeller of a centrifugal pump and can alsobe described as being spiral. However, the leads 22A can be formed indifferent configurations than the one shown (e.g., counter clock wisespiral, spoke pattern). Also, the contact 14A can include a lesser, or agreater number of leads 22A, with at least two or more leads necessaryto support the support member 21A.

[0053] With the leads 22A having a spiral configuration the supportmember 21A can move in a z-direction into the recess 20A, as the bumpedcontact 16 is pressed into the contact 14A by an external biasing force.During movement of the support member 21A into the recess 20A, a torqueis exerted on the support member 21A by the leads 22A. In addition, thesupport member 21A twists (i.e., rotates) about the longitudinal axis29A of the contact 14A. This twisting motion also rotates the supportmember 21A relative to the bumped contact 16, such that the peripheraledge 27A of the opening 26A penetrates native oxide layers that may bepresent on the bumped contact 16. This insures that the underlying metalof the bumped contact 16 is contacted such that a low resistanceelectrical connection is made.

[0054] Preferably the leads 22A comprise a highly conductive metal suchas aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver,platinum, palladium, tantalum, molybdenum, or alloys of these metals. Asshown in FIG. 2B, the leads 22A can also include an outer layer 31A,which comprises a material selected to provide a non-bonding surface forthe bumped contacts 16. For example, for bumped contacts 16 formed ofsolder, the outer layer 31A can comprise a metal that is not solderwettable. Suitable metals include Ti, TiSi₂ and Al. Rather than metal,the outer layer 31A can comprise a conductive polymer selected toprovide a non-bonding surface. Suitable conductive polymers includecarbon films and metal filled silicone.

[0055] As also shown in FIG. 2B, in the contact 14A, the leads 22A areformed on the polymer film 23 which is attached to the substrate 12. Thepolymer film 23 can be similar to multi layered TAB tape such as “ASMAT”manufactured by Nitto Denko. Alternately as will be further explained,the leads 22A can be formed directly on the substrate 12A using ametallization process such as CVD or electrodeposition.

[0056] The polymer film 23 comprises a thin flexible polymer such aspolyimide. The leads 22A and support member 21A can be formed bydepositing (e.g., electrodeposition) or attaching (e.g., lamination) ametal layer to the polymer film 23 and then patterning the metal layer.In addition, the polymer film 23 includes openings 33A (FIG. 2A) thatcorrespond in size and shape to the recesses 20A. The openings 33Aprovide access to the contact 14A for the bumped contact 16.

[0057] As also shown in FIG. 2B, the contact 14A includes conductors 30Aformed on a first surface of the substrate 12, and conductors 34A formedon a second opposing surface of the substrate 12. The conductors 30A andthe conductors 34A can comprise a same metal as the leads 22A andsupport member 21A. As shown in FIG. 2D, conductive vias 32Aelectrically connect the conductors 30A to the conductors 34A. Theconductive vias 32A comprise through openings in the substrate 12 atleast partially filled with a metal or conductive polymer. Theconductive vias 32A are electrically insulated from the substrate 12 bythe insulating layer 24A.

[0058] As also shown in FIGS. 2B and 2D, the conductive polymer layer 25electrically connects the conductors 30A on the substrate 12 to theleads 22A on the polymer film 23. The conductive polymer layer 25 cancomprise a metal filled silicone, a carbon filled ink, or an isotropicor anisotropic adhesive. Suitable conductive polymers are sold by A.I.Technology, Trenton, N.J.; Sheldahl, Northfield, Minn.; 3M, St. Paul,Minn.

[0059] As shown in FIG. 2C, the conductors 34A are in electricalcommunication with a bonding pad 35A formed on the second surface of thesubstrate 12. A terminal contact 36A is attached to the bonding pad 35A.The terminal contact 36A provides a connection point from the outside tothe contact 14A. The terminal contact 36A can comprise a metal ballattached to the bonding pad 35A using a suitable bonding process such assoldering, brazing, or welding. Alternately other types of terminalcontacts 36A such as planar pads, pins or shaped leads can be employedin place of metal balls.

[0060] Referring to FIGS. 3A and 3B, the contact 14A is illustratedduring electrical engagement of the bumped contact 16 on the component18. During electrical engagement an external biasing force F is exertedon the component 18, or alternately on the interconnect 10 to bias thecomponent 18 against the interconnect 10. As will be further explained,the biasing force F is generated by a testing apparatus on which theinterconnect 10 is mounted.

[0061] Prior to engaging the contact 14A, the bumped contact 16 isaligned with the opening 26A in the support member 21A of the contact14A. As will be further explained alignment can be accomplished with analignment fence or using optical alignment techniques. As the bumpedcontact 16 makes initial contact with the support member 21A the opening26A helps to center and retain the bumped contact 16.

[0062] As shown in FIG. 3B, following initial contact, the component 18and bumped contact 16 are overdriven in the z-direction into the recess20A. At the same time the leads 22A flex and twist about thelongitudinal axis 29A in a clockwise direction. The support member 21Aalso twists relative to the bumped contact 16 such that the peripheraledge 27A of the opening 26A penetrates and forms a peripheral groove inthe bumped contact 16. In addition, the movement of the bumped contacts16 into the recesses 20A helps to compensate for variations in the sizeand planarity of the bumped contacts 16. For example, bumped contacts 16that have a lesser height will not descend into the recess 20A by thesame amount as bumped contacts 16 with a greater height. In general, theamount of travel z of the support member 21A is a function of the depthX (FIG. 3B) of the recess 20A.

[0063] Referring to FIGS. 4A and 4B, an alternate embodiment contact 14Cis illustrated. The contact 14C is constructed substantially aspreviously described for contact 14A. However, a support member 21C forthe contact 14C comprises a solid plate with a peripheral blade 37. Theblade 37 functions in the same manner as the opening 26A (FIG. 3A) andperipheral edge 27A (FIG. 3A) previously described to penetrate thebumped contact 16. Also in the contact 14C, cantilevered leads 22C areextensible due to scallops 39 formed therein. The extensible leads 22Cfacilitate movement of the support member 21C into a recess 20C of thecontact 14C.

[0064] Referring to FIGS. 4C and 4D, an alternate embodiment contact 14Dis illustrated. The contact 14D includes a recess 20D and a supportmember 21D suspended over the recess 20D. The support member 21Dincludes an opening 26D with a peripheral edge 27D. The contact 14D alsoincludes extensible cantilevered leads 22D having a serpentineconfiguration. The contact 14D functions substantially the same aspreviously described contact 14A. However, in this embodiment the leads22D are formed directly on an insulating layer 24D on the substrate 12,rather than on a separate polymer film 23 (FIG. 4B) attached to thesubstrate 12.

[0065] Referring to FIGS. 5A and 5B, alternate embodiment contact 14B isillustrated. The contact 14B includes a support member 21B having anopening 16B with a peripheral edge 27B. In addition, the contact 14Bincludes four spring segment leads 22B formed on the substrate 12 inelectrical communication with a pattern of conductors 30B on the firstsurface of the substrate 12. The contact 14B also includes conductivevias 32B in the substrate 12, conductors 34B formed on the secondsurface of the substrate 12, and a terminal contact 36B formed on abonding pad 35B substantially as previously described. In addition,electrically insulating layers 24B are formed on exposed surfaces of thesubstrate 12 and within the conductive via 32B, substantially aspreviously described.

[0066] In this embodiment, the contact 14B does not include a recess inthe substrate 12. Rather the support member 21B is suspended on thesubstrate 12 by the spring segment leads 22B. However, the supportmember 21B is able to move in a z-direction towards the substrate 12upon engagement with the bumped contact 16 (FIG. 3A) under an externalbiasing force F (FIG. 3A). In addition, the spring segment leads 22Bhave a spiral, or twisted configuration, substantially as previouslydescribed for leads 22A (FIG. 2A). The spring segment leads 22B thusexert a torque on the support member 21B, and allow the support member21B to twist relative to the bumped contacts 16 substantially aspreviously described for contact 14A (FIG. 2A). Once the externalbiasing force F (FIG. 3A) and the bumped contact 16 are removed, thenatural resiliency of the spring segment leads 22B allows the supportmember 21B to return to the raised position. The amount of travel z ofthe support member 21B is a function of the height of the support member21B above the substrate 12.

[0067] Referring to FIGS. 6A-6G, steps in a method for fabricating theinterconnect 10 (FIG. 1) with the contact 14A (FIG. 2A) are illustrated.Initially as shown in FIG. 6A, the substrate 12 is provided. In theillustrative method, the substrate 12 comprises monocrystalline silicon.Preferably, the substrate 12 is provided as a wafer of material on whichmultiple interconnects 10 (FIG. 1) can be fabricated and then singulatedby saw cutting or shearing.

[0068] As also shown in FIG. 6A, the recesses 20A can be formed in thesubstrate using an etch process. For performing the etch process, a mask(not shown) such as a resist mask or a hard mask, can be formed on thesubstrate 12. The mask can include openings corresponding to the desiredsize and shape of the recesses 20A. A wet etchant can then be appliedthrough the openings in the mask to etch the recesses 20A to a desireddepth.

[0069] For example, the recesses 20A can be etched using an anisotropicetch process. With an anisotropic etch process, the recesses 20A willhave straight sidewalls, sloped at an angle of about 55° with respect tothe surface of the substrate 12. With the substrate 12 comprisingsilicon, one suitable etchant for performing an anisotropic etch is asolution of KOH:H₂O. Alternately, rather than an anisotropic etchprocess, an isotropic etch process can be used, to form the recesses20A. In this case, the recesses 20A will have curved sidewalls (notshown). With the substrate 12 comprising silicon, one suitable etchantfor performing an isotropic etch is a solution of HF, HNO₃ and H₂O.

[0070] If the substrate 12 comprises ceramic, the recesses 20A can alsobe formed using an etching process and a wet etchant such as HF. If thesubstrate 12 comprises a plastic the recesses 20A can be formed using amicro molding process, or a laser machining process.

[0071] As also shown in FIG. 6A, openings 38 can be formed for theconductive vias 32A. One method for forming the openings 38 is lasermachining. A suitable laser machining apparatus for forming the openings38 is manufactured by General Scanning of Sommerville, Mass. and isdesignated a Model No. 670-W. Another suitable laser machining apparatusis manufactured by Synova S.A., Lausanne, Switzerland.

[0072] A representative diameter of the openings 38 can be from 10 μm to2 mils or greater. A representative fluence of a laser beam for formingthe openings 38 with the substrate 12 comprising silicon and having athickness of about 28 mils, is from 2 to 10 watts/per opening at a pulseduration of 20-25 ns and at a repetition rate of up to several thousandper second. The wavelength of the laser beam can be a standard infraredor green wavelength (e.g., 1064 nm-532 nm), or any wavelength that willinteract with and heat silicon.

[0073] Following formation of the recesses 20A and openings 38, theinsulating layers 24A (FIGS. 2B and 2D) can be formed on exposedsurfaces of the substrate 12, and in the recesses 20A and openings 38.For simplicity, the insulating layers 24A are not shown in FIGS. 6A-6G.Also, if the substrate 12 comprises an electrically insulating materialsuch as ceramic or plastic, the insulating layers 24A are not required.

[0074] The insulating layers 24A (FIGS. 2B and 2D) can comprise anelectrically insulating material, such as SiO₂ or Si₃N₄ deposited usinga process such as CVD. A SiO₂ layer can also be grown using an oxidizingatmosphere such as steam and O₂ at an elevated temperature (e.g., 950°C.). Alternately, the insulating layers 24A can comprise a depositedpolymer such as polyimide. One method for depositing a polymer is with aspin on process. Depending on the material, a representative thicknessof the insulating layers 24A can be from about 100 Å to several mils.

[0075] Next, as shown in FIG. 6B, the conductors 30A can be formed onthe substrate 12 using a suitable metallization process (e.g., CVD,patterning, etching). Preferably, the conductors 30A comprise a highlyconductive metal such as aluminum, titanium, nickel, iridium, copper,gold, tungsten, silver, platinum, palladium, tantalum, molybdenum, oralloys of these metals.

[0076] Next, as shown in FIG. 6C, a conductive material can be depositedwithin the openings 38 to form the conductive vias 32A. The conductivematerial can comprise a metal, such as aluminum, titanium, nickel,iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum,molybdenum, or alloys of these metals. The metal can be deposited withinthe openings 38 using a deposition process, such as CVD, electrolyticdeposition or electroless deposition. Alternately, a solder alloy can bescreen printed into the openings 38, or injected by capillary action, orwith a vacuum system using a hot solder wave. In addition, theconductive material can comprise plugs that completely fill the openings38, or alternately can comprise layers that cover just the insidesurfaces or sidewalls of the opening 38.

[0077] Also, rather than being a metal, the conductive material cancomprise a conductive polymer, such as a metal filled silicone, a carbonfilled ink, or an isotropic or anisotropic adhesive. Suitable conductivepolymers are sold by A.I. Technology, Trenton, N.J.; Sheldahl,Northfield, Minn.; 3M, St. Paul, Minn. A conductive polymer can bedeposited within the openings 38, as a viscous material, and then curedas required. A suitable deposition process, such as screen printing, orstenciling, can be used to deposit the conductive polymer into theopenings 38.

[0078] At the same time the conductive material is deposited in theopenings 38, the conductors 34A and the pads 35A can be formed on thesecond side of the substrate 12. A suitable mask (not shown) can be usedto form the conductors 34A and the pads 35A with a desired thickness andperipheral shape. Alternately, the conductors 34A and the pads 35A cancomprise a different material than the conductive material for theconductive vias 32A, and can be formed using a separate deposition ormetallization process. For example, the conductors 34A and the pads 35Acan comprise a bondable or solderable metal such as copper or aluminum,while the conductive material can comprise a material such as nickel.

[0079] Next, as shown in FIG. 6D, the conductive polymer layer 25 can beformed on the substrate 12 using a suitable deposition process such asscreen printing or stenciling. The conductive polymer layer 25 willelectrically connect the conductors 30A on the substrate 12 to the leads22A (FIG. 6E) on the polymer film 23 (FIG. 6E). In addition, theconductive polymer layer 25 functions to attach the polymer film 23(FIG. 6E) to the substrate 12. The conductive polymer layer 25 cancomprise a metal filled silicone, a carbon filled ink, an isotropicadhesive, or an anisotropic adhesive. Suitable conductive polymermaterials are sold by A.I. Technology, Trenton, N.J.; Sheldahl,Northfield, Minn.; 3M, St. Paul, Minn. Alternately rather than beinginitially applied to the substrate 12, the conductive polymer layer 25can be initially applied to the polymer film 23.

[0080] Next, as shown in FIG. 6E, the polymer film 23 can be attached tothe substrate 12 using the conductive polymer layer 25. Depending on thematerial, the conductive polymer layer 25 can be cured using heat andcompression as required. Prior to attaching the polymer film 23 to thesubstrate 12, the support members 21A and leads 22A can be aligned withthe recesses 20A in the substrate 12. As previously explained, thepolymer film 23 can be similar to multi layered TAB tape, and can befabricated using techniques that are known in the art. For example, thesupport members 21A and leads 22A can be formed in a desiredconfiguration on a polyimide film using an electrodeposition process.Also required features such as the opening 26A (FIG. 6G), peripheraledge 27A (FIG. 6G) or blades 37 (FIG. 4B) can be formed as required.

[0081] As also shown in FIG. 6E, the terminal contacts 36A can beattached to the pads 35A using a soldering, brazing or welding process.The terminal contacts 36A can be formed of a relatively hard metal suchas nickel, copper, beryllium copper, alloys of nickel, alloys of copper,alloys of beryllium copper, nickel-cobalt-iron alloys and iron-nickelalloys. These relatively hard metals will allow the terminal contacts36A to resist wear and deformation during continued usage of theinterconnect 10. The terminal contacts 36A can also comprise a basemetal and an outer layer formed of a non-oxidizing metal such as gold,silver, copper or palladium. For some applications, the terminalcontacts 36A can comprise a solder alloy such as 95% Pb/5% Sn, 60%Pb/40% Sn, 63% In/37% Sn, or 62% Pb/36% Sn/2% Ag. The terminal contacts36A can also be a conductive polymer such as an isotropic or anisotropicadhesive.

[0082] One method for attaching the terminal contacts 36A to the pads35A is by bonding pre-fabricated metal balls to the pads 35. Forexample, pre-fabricated metal balls are manufactured by Mitsui ComtekCorp. of Saratoga, Calif. under the trademark “SENJU SPARKLE BALLS”. Themetal balls can be attached to the pads 35 by soldering, laser reflow,brazing, welding, or applying a conductive adhesive. A solder ballbumper can also be used to bond the terminal contacts 36A to the pads35. A suitable solder ball bumper is manufactured by Pac Tech PackagingTechnologies of Falkensee, Germany. The terminal contacts 36A can alsobe formed on the pads 35 using a conventional wire bonder apparatusadapted to form a ball bond, and then to sever the attached wire. Theterminal contacts 36A can also be formed by electrolytic deposition orelectroless deposition of a metal to form bumps.

[0083] A representative diameter for the terminal contacts 36A can befrom about 4 mils to 50 mils or more. A pitch of the terminal contacts36A can be from about 6 mils to 50 mils or more. In addition, the pitchof the pads 35 and the terminal contacts 36A can exactly match the pitchof the contacts 14A or can be different than the contacts 14A.

[0084] Referring to FIGS. 7A-7H, steps in a method for fabricating theinterconnect 10 (FIG. 1) with the contact 14D (FIG. 4C) are illustrated.Initially as shown in FIG. 7A, the substrate 12 can be provided and therecesses 20A formed substantially as previously described.

[0085] Next, as shown in FIG. 7B, the recesses 20A can be filled with apolymer material 40. One suitable polymer material is a thick filmresist sold by Shell Chemical under the trademark “EPON RESIN SU-8”. Aconventional resist coating apparatus, such as a spin coater, or ameniscus coater, along with a mask or stencil, can be used to depositthe resist in viscous form into the recesses 20A. The resist can then beplanarized and cured as required. For example curing can be performed byheating to about 200° C. for about 30 minutes. Rather than a thick filmresist, the polymer material 40 can comprise another curable polymersuch as polyimide, or photoimageable polyimide.

[0086] As also shown in FIG. 7B, following filling of the recesses 20A,openings 38 for conductive vias 32D (FIG. 7C) can be formed in thesubstrate 12. The openings 38 can be formed using a laser machiningprocess as previously described. FIG. 7F illustrates the pattern of theopenings 38 relative to the recesses 20A.

[0087] Next, as shown in FIG. 7C, metal layers 42 can be formed on thepolymer material 40 and over the openings 38. FIG. 7G illustrates anexemplary layout for the metal layers 42. A deposition process, such asCVD or electrodeposition, can be used to form the metal layers 42.Preferably the metal layers 42 comprise a high yield strength metal,such as tungsten, titanium, nickel, platinum, iridium, or vanadium. Arepresentative thickness of the metal layers 42 can be from 1 μm to 100μm or more. As also shown in FIG. 7C, following (or prior to) depositionof the metal layers 42, the conductive vias 32D, conductors 34D, andpads 35D can be formed substantially as previously described.

[0088] Next, as shown in FIG. 7D, a mask 44 can be formed on the metallayers 42 and used to etch the metal layers 42 in a desired pattern. Themask 44 can comprise a conventional photoresist layer patterned using aconventional photolithography process. Depending on the material for themetal layers 42 a suitable wet etchant can be applied through openingsin the mask 44 to etch the metal layers 42.

[0089] Next, as shown in FIG. 7E, the mask 44 can be removed using asuitable stripper. In addition, the polymer material 40 within therecesses 20A can be removed using a suitable stripper. One suitablestripper for the previously identified thick film resist comprises hotNMP. As also shown in FIG. 7E, terminal contacts 36D can be attached tothe pads 35D, substantially as previously described.

[0090] As shown in FIG. 7H, the metal layers 42 (FIG. 7C) have beenetched to form support members 21D and cantilevered leads 22D inelectrical communication with the conductive vias 32D. If desired, theleads 22D can have a serpentine or scalloped configuration as previouslydescribed. In addition, other required features such as the openings 26D(or the blades 37—FIG. 4B) can be formed during the etching process.Some features, such as the blades 37 (FIG. 4B) may require additionalmasks and etch steps.

[0091] Optionally, the support members 21D can include a surface thatwill not bond to the bumped contacts 16. This can be a separatedeposition process in which a separate metal or conductive polymer layeris applied, or the metal layers 42 can comprise a non bonding metal.Suitable non bonding metals for bumped contacts 16 formed of solderinclude Ti, TiSi₂ or Al. Suitable non bonding conductive polymersinclude carbon films and metal filled silicone.

[0092] Referring to FIGS. 8A-8I, steps in a method for fabricating theinterconnect 10 (FIG. 1) with the contact 14B (FIG. 5A) are illustrated.Initially, as shown in FIG. 8A, the substrate 12 can be provided. Asbefore the substrate 12 can comprise silicon, ceramic, or plastic.

[0093] As also shown in FIG. 8A, a polymer layer 46 can be blanketdeposited on the substrate 12. The polymer layer 46 can comprise thepreviously identified thick film resist sold by Shell Chemical under thetrademark “EPON RESIN SU-8”. This resist can be deposited in layers to athickness of from about 3-50 mils. The resist also includes an organicsolvent (e.g., gamma-butyloracton), and a photoinitiator.

[0094] A conventional resist coating apparatus, such as a spin coater,or a meniscus coater can be used to deposit the resist in viscous formonto the first surface of the substrate 12. The deposited resist canthen be partially hardened by heating to about 95° C. for about 15minutes or longer.

[0095] Next, as shown in FIG. 8B, the polymer layer 46 can be exposedand developed such that polymer bumps 47 are formed. As also shown inFIG. 8B, the openings 38 for conductive vias 32B can be formed in thesubstrate 12 as previously described.

[0096] The polymer bumps 47 are sized and shaped to form the supportmembers 21B (FIG. 8I) and leads 22B (FIG. 8I) for the contacts 14B (FIG.8I). A representative height for the polymer bumps 47 can be about 10-25mils, and a representative width can be about 5-50 mils. Forillustrative purposes, the leads 22B for the contacts 14B are shown in abowed configuration when viewed from the side (e.g., FIG. 5B). However,it is to be understood that the leads 22B can have other configurations,such as a substantially straight when viewed from the side.

[0097] Exposure of the polymer layer 46 to form the polymer bumps 47 canbe with a conventional UV mask writer using a suitable UV dose. Arepresentative UV dose for the previously described resist formulationis about 165 mJ/cm². One suitable developer for the resist comprises asolution of PGMEA (propyleneglycol-monomethylether-acetate). Followingdevelopment the resist can be fully hardened. A “full cure” can beperformed with a hard bake at about 200° C. for about 30 minutes. Ratherthan a thick film resist, the polymer layer 46 can comprise anothersuitable curable polymer such as polyimide, or photoimageable polyimide.

[0098] Next, as shown in FIG. 8C, the conductive vias 32B, conductors34B, and pads 35B can be formed as previously described. In addition,metal layers 48 are formed on the polymer bumps 47 and on the conductivevias 32B. The metal layers 48 can be deposited using a suitabledeposition process such as such as CVD or electrodeposition. Preferablythe metal layers 48 comprise a high yield strength metal, such astungsten, titanium, nickel, platinum, iridium, or vanadium. Arepresentative thickness of the metal layers 48 can be from 1 μm to 100μm or more.

[0099] Next, as shown in FIG. 8D, resist masks 49 are formed on themetal layers 48. The resist masks 49 have a thickness that is greaterthan a height of the polymer bumps 47. The resist masks 49 can comprisethe previously identified thick film resist used to form the polymerbumps 47. In addition, the resist masks 49 are developed with a requiredpattern for forming the conductors 30B (FIG. 8E), the support members21B (FIG. 8I), and the leads 22B (FIG. 8I) for the contacts 14B. Usingthe resist masks 49, the metal layers 48 are etched to form theconductors 30B, the support members 21B and the leads 22B. Depending onthe metal, a suitable wet etchant can be used to etch the metal layers48 through openings in the resist masks 49.

[0100] Next, as shown in FIG. 8E, the resist masks 49 can be strippedusing a suitable stripper. One suitable stripper for the previouslyidentified thick film resist comprises hot NMP. Following stripping ofthe resist masks 49 and as shown in FIG. 8F, the polymer bumps 47 canalso be stripped using a suitable stripper. Depending on the materialused to form the polymer bumps 47 and resist masks 49 the same strippercan be used and the stripping step can be continuous. As anotheralternative a plasma etch process can be used to remove the resist masks49 and polymer bumps 47. As also shown in FIG. 8F, the terminal contacts36B can be attached to the pads 35B as previously described.

[0101] Die Level Test System

[0102] Referring to FIGS. 9A-9C, a test carrier 80 constructed using aninterconnect 10A constructed in accordance with the invention isillustrated. The test carrier 80 is adapted to temporarily packagesemiconductor components 18A for test and burn-in. The semiconductorcomponents 18A can comprise either bare dice, or chip scale packages.The semiconductor components 18A include bumped contacts 16, such assolder balls, in electrical communication with the integrated circuitscontained on the components 18A.

[0103] The test carrier 80 includes the interconnect 10A, and a forceapplying mechanism 82. The interconnect 10A includes contacts 14Dadapted to make temporary electrical connections with the bumpedcontacts 16 on the components 18A. The contacts 14 can be formed aspreviously described for contacts 14A (FIGS. 2A), or contacts 14B (FIG.5A), or contacts 14C (FIG. 4A), or contacts 14D (FIG. 4C) . In addition,the interconnect 10A includes conductive vias 32 in electricalcommunication with the contacts 14. The conductive vias 32 can be formedas previously described for conductive vias 32A (FIG. 2D).

[0104] The interconnect 10A also include terminal contacts 36 such asmetal balls as previously described. Alternately other types of terminalcontacts such as pins, flat pads, or shaped wires can be employed. Theterminal contacts 36 are adapted to electrically engage matingelectrical connectors (not shown) on a test apparatus 96 (FIG. 9A), suchas a burn-in board. The test apparatus 96 includes, or is in electricalcommunication with test circuitry 98, adapted to apply test signals tothe integrated circuits contained on the components 18A, and to analyzethe resultant signals. The test carrier 80, test apparatus 96, and testcircuitry 98 form a test system 100 (FIG. 9A).

[0105] The test carrier 80 also includes an alignment member 86 adaptedto align the bumped contacts 16 on the components 18A, to the contacts14 on the interconnect 10A. The alignment member 86 includes openings 88configured to contact the peripheral edges of the components 18A toguide the components 18A onto the contacts 14. The alignment member 86can be constructed, as described in U.S. Pat. No. 5,559,444, entitled“METHOD AND APPARATUS FOR TESTING UNPACKAGED SEMICONDUCTOR DICE”,incorporated herein by reference. As another alternative, the alignmentmember 86 can be eliminated and the components 18A can be aligned withthe contacts 14 using an optical alignment technique. Such an opticalalignment technique is described in U.S. Pat. No. 5,796,264, entitled“APPARATUS FOR MANUFACTURING KNOWN GOOD SEMICONDUCTOR DICE”, which isincorporated herein by reference.

[0106] As shown in FIGS. 9A and 9B, the force applying mechanism 82includes a clamp member 90 which attaches to the interconnect 10A, and aplurality of biasing members 92 for pressing the components 18A againstthe contacts 14. In the illustrative embodiment, the biasing members 92comprise elastomeric blocks formed of a polymer material such assilicone, butyl rubber, flourosilicone, or polyimide. Alternately thebiasing members 92 can comprise steel leaf springs. The clamp member 90includes tabs 94 for engaging the interconnect 10A to secure the clampmember 90 to the interconnect 10A.

[0107] In the illustrative embodiment, the clamp member 90 attachesdirectly to the interconnect 10A which is configured to form a base forthe test carrier 80. However, the test carrier 80 can include a separatebase, and the interconnect 10A can be mounted to the base as isdescribed in U.S. Pat. No. 5,519,332 to Wood et al.; U.S. Pat. No.5,541,525 to Wood et al.; U.S. Pat. No. 5,815,000 to Farnworth et al.;and U.S. Pat. No. 5,783,461 to Hembree, all of which are incorporatedherein by reference.

[0108] Wafer Level Test System

[0109] Referring to FIG. 10, a wafer level system 100W suitable fortesting a semiconductor wafer 102 having bumped contacts 16 isillustrated. The wafer level test system 100W includes an interconnect10W constructed in accordance with the invention as previouslydescribed, and mounted to a testing apparatus 96W.

[0110] The testing apparatus 96W includes, or is in electricalcommunication with test circuitry 98. The testing apparatus 96W can be aconventional wafer probe handler, or probe tester, modified for use withthe interconnect 10W. Wafer probe handlers and associated test equipmentare commercially available from Electroglass, Advantest, Teradyne,Megatest, Hewlett-Packard and others. In this system 100W, theinterconnect 10W takes the place of a conventional probe card.

[0111] The interconnect 10W includes contacts 14W configured toestablish electrical communication with the bumped contacts 16 on thewafer 102. The contacts 14W can be formed as previously described forcontacts 14A (FIGS. 2A), or contacts 14B (FIG. 5A), or contacts 14C(FIG. 4A), or contacts 14D (FIG. 4C). In addition, the interconnect 10Aincludes conductive vias 32W in electrical communication with thecontacts 14W. The conductive vias 32 can be formed as previouslydescribed for conductive vias 32A (FIG. 2D).

[0112] The testing apparatus 96W also includes a wafer chuck 106configured to support and move the wafer 102 in x, y and z directions asrequired. In particular, the wafer chuck 106 can be used to step thewafer 102 so that the dice on the wafer 102 can be tested in groupsuntil all of the dice have been tested. Alternately, the interconnect10W can be configured to contact all of the bumped contacts 16 for allof the dice on the wafer 102 at the same time. Test signals can then beselectively applied and electronically switched as required, to selecteddice on the wafer 102.

[0113] As also shown in FIGS. 10, the interconnect 10W can mount to aprobe card fixture 108 of the testing apparatus 96W. The probe cardfixture 108 can be similar in construction to a conventional probe cardfixture commercially available from manufacturers such as Packard HughesInterconnect and Wentworth Laboratories. The probe card fixture 108 canbe formed of an electrically insulating material such as FR-4 orceramic. In addition, the testing apparatus 96W can include a forceapplying mechanism in the form of multiple spring loaded electricalconnectors 104 associated with the probe card fixture 108. The springloaded electrical connectors 104 are in electrical communication withthe testing circuitry 98.

[0114] The spring loaded electrical connectors 104 can be formed in avariety of configurations. One suitable configuration is known as a“POGO PIN” connector. This type of electrical connector includes aspring loaded pin adapted to contact and press against a flat surface toform an electrical connection. Pogo pin connectors are manufactured byPogo Instruments, Inc., Kansas City, Kans. The spring loaded electricalconnectors 104 can also comprise wires, pins or cables formed as springsegments or other resilient members.

[0115] In this embodiment the spring loaded electrical connectors 104electrically contact pads 35W formed on the interconnect 10W. Thisarrangement provides separate electrical paths from the testingcircuitry 98, through the spring loaded electrical connectors 104,through the pads 35W, through the conductive vias 32W and through thecontacts 14W to the bumped contacts 16. During a test procedure, testsignals can be applied to the integrated circuits on the wafer 102 usingthese separate electrical paths.

[0116] In addition to establishing electrical communication with theinterconnect 10W, the spring loaded electrical connectors 104 alsoprovide a mechanical force necessary for biasing the interconnect 10Wagainst the wafer 102. Further details of a wafer level system similarto the system 100W are contained in U.S. patent application No.08/797,719, filed Feb. 10, 1997, entitled “PROBE CARD FOR SEMICONDUCTORWAFERS AND METHOD AND SYSTEM FOR TESTING WAFERS” which is incorporatedherein by reference.

[0117] Thus the invention provides an improved test interconnect fortesting semiconductor components having bumped contacts. Theinterconnect include contacts designed to provide a reliable electricalconnection to the bumped contacts with a minimal application of contactforce. In addition, the contacts are constructed to move in thez-direction to accommodate variations in the size or planarity of thebumped contacts and to twist relative to the bumped contacts topenetrate oxide layers thereon.

[0118] While the invention has been described with reference to certainpreferred embodiments, as will be apparent to those skilled in the art,certain changes and modifications can be made without departing from thescope of the invention as defined by the following claims.

What is claimed is:
 1. An interconnect for testing a semiconductorcomponent comprising: a substrate comprising a recess; and a contact onthe substrate configured to electrically engage a bumped contact on thecomponent, the contact comprising a support member for supporting thebumped contact proximate the recess, and a plurality of leads on thesubstrate attached to the support member, the leads configured to permitthe support member to move into the recess and to twist the supportmember relative to the bumped contact during movement into the recess.2. The interconnect of claim 1 wherein the leads are arranged in aspiral relative to an axis of the contact.
 3. The interconnect of claim1 wherein the leads have an extensible configuration.
 4. Theinterconnect of claim 1 wherein the support member comprises an openinghaving a peripheral edge for penetrating the bumped contact.
 5. Theinterconnect of claim 1 wherein the support member comprises at leastone projection for penetrating the bumped contact.
 6. An interconnectfor testing a semiconductor component comprising: a substrate comprisinga recess and a plurality of conductors; a polymer film attached to thesubstrate; and a contact on the substrate configured to electricallyengage a bumped contact on the component, the contact comprising asupport member proximate the recess for supporting the bumped contact,and a plurality of leads on the polymer film in electrical communicationwith the conductors and attached to the support member, the supportmember and leads configured to move within the recess and to rotaterelative to the bumped contact during movement into the recess.
 7. Theinterconnect of claim 6 wherein the leads are electrically connected tothe conductors using a conductive adhesive layer.
 8. The interconnect ofclaim 6 further comprising a plurality of conductive vias in thesubstrate in electrical communication with the conductors and with aterminal contact on the substrate.
 9. The interconnect of claim 6wherein the support member comprises a non-bonding outer surfacerelative to the bumped contact.
 10. An interconnect for testing asemiconductor component comprising: a substrate comprising a recess anda plurality of conductors; a polymer film attached to the substratecomprising an opening aligned with the recess; and a contact configuredto electrically engage a bumped contact on the component, the contactcomprising a plurality of leads on the polymer film in electricalcommunication with the conductors, and a support member attached to theleads and suspended proximate the recess, the support member locatedproximate the opening and configured to move into the recess, the leadsconfigured to exert a torque on the support during movement into therecess.
 11. The interconnect of claim 10 further comprising a conductivepolymer on the substrate electrically connecting the leads to theconductors.
 12. The interconnect of claim 10 wherein the support membercomprises an opening with a peripheral edge for penetrating the bumpedcontact.
 13. The interconnect of claim 10 wherein the support membercomprises a projection for penetrating the bumped contact.
 14. Theinterconnect of claim 10 wherein the conductors are formed on a firstsurface of the substrate and the substrate comprises a plurality ofconductive vias in electrical communication with the conductors and witha terminal contact on a second opposing surface of the substrate.
 15. Aninterconnect for testing a semiconductor component comprising: asubstrate; and a contact on the substrate configured to electricallyengage a bumped contact on the component, the contact comprising: arecess in the substrate; a plurality of leads on the substratecantilevered on the recess and having a generally spiral configurationwith respect to an axis of the contact; and a support member attached tothe leads configured to support the bumped contact proximate the recess,to move the bumped contact within the recess with an external biasingforce, and to twist about the axis during movement into the recess topenetrate the bumped contact.
 16. The interconnect of claim 15 whereinthe support member comprises an opening for retaining the bumped contactand a peripheral edge for penetrating the bumped contact.
 17. Theinterconnect of claim 15 wherein the support member comprises aprojection for retaining and penetrating the bumped contact.
 18. Theinterconnect of claim 15 wherein the leads comprise a polymer filmattached to the substrate.
 19. The interconnect of claim 15 wherein thesubstrate comprises a conductor and a conductive via in electricalcommunication with the leads.
 20. The interconnect of claim 15 whereinthe leads have an extensible configuration.
 21. The interconnect ofclaim 14 wherein the leads have a serpentine configuration.
 22. Theinterconnect of claim 14 wherein the support member comprises anon-bonding conductive polymer outer layer.
 23. The interconnect ofclaim 14 wherein the support member comprises a material selected fromthe group consisting of Ti, TiSi₂ and Al.
 24. An interconnect fortesting a semiconductor component comprising: a substrate; and a contacton the substrate for electrically engaging a bumped contact on thecomponent, the contact comprising a support member for supporting thebumped contact, and a plurality of spring segment leads on the substrateattached to the support member, the leads configured to permit thesupport member to move towards the substrate during electricalengagement of the bumped contact and to rotate the support member aboutan axis of the contact during movement thereof.
 25. The interconnect ofclaim 24 wherein the substrate further comprises a conductor on thesubstrate and a conductive via in the substrate in electricalcommunication with the leads.
 26. The interconnect of claim 24 whereinthe support member comprises an opening having a peripheral edge forpenetrating the bumped contact.
 27. The interconnect of claim 24 whereinthe support member comprises at least one projection for penetrating thebumped contact.
 28. The interconnect of claim 24 wherein the leadscomprise extensible members.
 29. The interconnect of claim 24 whereinthe leads have a serpentine configuration.
 30. An interconnect fortesting a semiconductor component comprising: a substrate; a contact onthe substrate for electrically engaging a bumped contact on thecomponent, the contact comprising: a support member with an openingtherein having a peripheral edge for retaining the bumped contact; and aplurality of leads attached to the substrate for suspending the supportmember on the substrate, the leads comprising spring segments having agenerally spiral configuration configured to twist the support memberabout an axis during movement towards the substrate to allow theperipheral edge to penetrate the bumped contact.
 31. The interconnect ofclaim 30 wherein the leads comprise a metal selected from the groupconsisting of tungsten, titanium, nickel, platinum, iridium, andvanadium.
 32. The interconnect of claim 30 wherein the support membercomprises a non-bonding outer layer.
 33. The interconnect of claim 30wherein the support member comprises a conductive polymer outer layer.34. A method for fabricating an interconnect for testing a semiconductorcomponent comprising: providing a substrate; forming a plurality ofconductors on the substrate; forming a recess in the substrate;providing a polymer film comprising an opening therein and a supportmember proximate to the opening configured to support a bumped contacton the component, and a plurality of leads attached to the supportmember, the leads configured to permit the support member to move in az-direction into the recess and to twist the support member relative tothe bumped contact during movement thereof; aligning the support memberwith the recess; and attaching the film to the substrate with the leadsin electrical communication with the conductors.
 35. The method of claim34 wherein the attaching step comprises forming a conductive polymerlayer between the conductors and the leads.
 36. The method of claim 34further comprising providing the support member with an opening having aperipheral edge for penetrating the bumped contact.
 37. The method ofclaim 34 further comprising providing the support member with anon-bonding surface relative to the bumped contact.
 38. A method forfabricating an interconnect for testing a semiconductor componentcomprising: providing a substrate; forming a recess in the substrate;forming a polymer material in the recess; forming a metal layer on thesubstrate and polymer material; etching the metal layer to form acontact comprising a support member for electrically engaging a bumpedcontact on the component and a plurality of leads configured to permitthe support member to move into the recess; and removing the polymermaterial from the recess.
 39. The method of claim 34 further comprisingforming a non-bonding outer layer on the metal layer prior to theetching step.
 40. The method of claim 34 wherein the non-bonding outerlayer comprises a material selected from the group consisting of Ti,TiSi₂, Al and conductive polymers.
 41. The method of claim 34 whereinthe etching step comprises forming the leads with a generally spiralconfiguration.
 42. The method of claim 34 wherein the etching stepcomprises forming the leads with an extensible configuration.
 43. Themethod of claim 34 wherein the metal layer comprise a metal selectedfrom the group consisting of tungsten, titanium, nickel, platinum,iridium, and vanadium.
 44. The method of claim 34 further comprisingforming an electrically insulating layer within the recess.
 45. Themethod of claim 34 wherein the substrate comprises silicon and formingthe recess comprises an anisotropic etch process.
 46. A method forfabricating an interconnect for testing a semiconductor componentcomprising: providing a substrate; forming a plurality of polymer bumpson the substrate; forming a metal layer on the polymer bumps and on thesubstrate; etching the metal layer to form a contact comprising asupport member for electrically engaging a bumped contact on thecomponent, and a plurality of leads attached to the support member andto the substrate; and following the etching step, removing the polymerbump from the substrate to form a contact comprising the support membersuspended on the substrate and the leads configured to permit thesupport member towards the substrate during electrical engagement of thebumped contact.
 47. The method of claim 46 further comprising during theetching step forming the support member with a peripheral edge forpenetrating the bumped contact.
 48. The method of claim 46 furthercomprising during the etching step forming the support member with aprojection for penetrating the bumped contact.
 49. The method of claim46 further comprising during the etching step forming the leads in aspiral configuration configured to twist the support member relative tothe contact bumps during movement thereof towards the substrate.
 50. Themethod of claim 46 further comprising during the etching step formingthe leads in an extensible configuration.
 51. The method of claim 46further comprising forming a non-bonding outer layer on the supportmember.
 52. A system for testing a semiconductor component comprising: acarrier for retaining the semiconductor component; an interconnect onthe carrier comprising a substrate and a contact on the substrateconfigured to electrically engage a bumped contact on the component, thecontact comprising a support member for supporting the bumped contactproximate a recess in the substrate, and a plurality of leads on thesubstrate attached to the support member, the leads configured to permitthe support member to move into the recess and to twist the supportmember relative to the bumped contact during movement into the recess;and test circuitry in electrical communication with the leads forapplying test signals to the component.
 53. The system of claim 52wherein the component comprises an element selected from the groupconsisting of semiconductor dice, semiconductor packages andsemiconductor wafers.
 54. The system of claim 52 wherein the leadscomprise a polymer film attached to the substrate.
 55. A system fortesting a semiconductor component comprising: a carrier configured toretain the component; an interconnect on the carrier comprising: asubstrate; a recess in the substrate; a plurality of leads on thesubstrate cantilevered on the recess and having a generally spiralconfiguration with respect to an axis of the contact; and a supportmember attached to the leads configured to support the bumped contactproximate the recess, to move the bumped contact within the recess withan external biasing force, and to twist about the axis during movementinto the recess to penetrate the bumped contact.
 56. The system of claim55 wherein the interconnect further comprises a conductive via inelectrical communication with the leads and a terminal contactelectrically connectable to test circuitry.
 57. A system for testing asemiconductor component comprising: a carrier configured to retain thecomponent; an interconnect on the carrier comprising: a substrate; and acontact on the substrate for electrically engaging a bumped contact onthe component, the contact comprising a support member for supportingthe bumped contact, and a plurality of spring segment leads on thesubstrate attached to the support member, the leads configured to permitthe support member to move towards the substrate during electricalengagement of the bumped contact and to rotate the support member aboutan axis of the contact during movement thereof.
 58. The system of claim57 wherein the support member comprises a non-bonding outer layer.
 59. Asystem for testing a semiconductor component comprising: a wafer prober;an interconnect mounted to the wafer prober comprising: a substratecomprising a recess and a plurality of conductors; a polymer filmattached to the substrate; and a contact on the substrate configured toelectrically engage a bumped contact on the component, the contactcomprising a support member proximate the recess for supporting thebumped contact, and a plurality of leads on the polymer film inelectrical communication with the conductors and attached to the supportmember, the support member and leads configured to move within therecess and to rotate relative to the bumped contact during movement intothe recess.
 60. The system of claim 59 wherein the substrate comprises apad in electrical communication with the leads and the wafer probercomprises a spring loaded electrical connector configured to engage thepad.